In the formation of semiconductor devices, it is necessary to provide both desired electrical contact between certain regions of the devices formed and also to prevent contact between various other regions of the devices formed on the substrate. One technique for accomplishing this has been by using photoresist and masking techniques wherein those areas to be exposed for electrical contact are patterned in the photoresist, and then the pattern developed in the photoresist, to thereby expose the desired underlying regions. This technique normally requires several successive masks and thin film depositions and film etches to perform the entire process, and in this performance each succeeding mask must be precisely aligned to the previous photolithographic levels. However, as the technology advances, requiring the formation of smaller and smaller features, it is increasingly difficult to maintain precise overlay tolerance, with the result that even small misalignments of the masks will result in the exposure of small portions or "borders" of regions that are intended to remain covered. Hence, electrical connections, e.g. by an overlay deposition of a metal, will connect not only the desired locations, but also those exposed border portions of the undesired locations.
In the case of, for instance, SRAM cells, a limiting factor for shrinking the cells is the contact to diffusion with respect to the gate conductor and the wiring needed in conjunction with the contact. This limiting factor ensures that the diffusion contact does not electrically short to the gate conductor. Typical methods used to solve this problem are polysilicon cross-coupling incorporating a buried contact, which requires at least two critical masking levels, and tungsten stud and metal wiring, which also requires at least two critical masking levels and associated processing. Both of these techniques require a significant amount of silicon space, thus increasing the SRAM cell size.